1. Field of the Invention
The present invention relates to a logic circuit, and particularly to a logic circuit that generates exclusive OR (XOR) signal and exclusive NOR (XNOR) signal at the same time. The present invention also relates to a semiconductor device and a data processing system that include the logic circuit.
2. Description of Related Art
DDR4 (Double Data Rate 4), which is a next-generation standard of DRAM (Dynamic Random Access Memory), is expected to have more input/output errors due to a higher operational speed thereof. Therefore, a CRC (Cyclic Redundancy Check) code is added to input data and output data that are transferred via data input/output terminals.
The CRC code is generated in both a transmitter and receiver of data signals. A first CRC code that is generated by the transmitter on the basis of data signals is transmitted to the receiver along with the data signals. The receiver generates a second CRC code on the basis of the data signals received, and compares the second CRC code with the received first CRC code. If the first CRC code matches the second CRC code, then the receiver accepts the data signals. If the first CRC code does not match the second CRC code, then the receiver notifies the transmitter of the fact that the first CRC code does not match the second CRC code.
The data signals that are input and output in DDR4 DRAM may be 72-bit data including 64-bit read or write data and 8-bit DBI (Data Bus Inversion) data. The CRC code is made up of eight bits, and is generated based on a plurality of bits selected from among the 72 bits. To generate the CRC code, exclusive OR circuit is used. More specifically, two sets of a plurality of bits selected are selected, and the exclusive OR signal of those selected is calculated; then two calculation results are selected, and the exclusive OR signal of those selected is calculated. The above calculation process is repeated until 1-bit data is eventually obtained. The CRC code that is calculated as described above is “1” at a time when the number of bits equal to “1” among a plurality of bits selected is odd; otherwise the CRC code is “0.”
In generating the CRC codes, exclusive OR operation is frequently used as in the above case, requiring a large number of XOR gate circuits. As for the specific circuit configuration of the XOR gate circuits, various types are known. Some examples are disclosed in: Ashok K. Goel, “VLSI Design”, [online], Michigan Technological University, [searched on Sep. 15, 2011], Internet <URL:http://www.ece.mtu.edu/faculty/goel/EE-4271/Project-5.pdf>; genji, “XOR Gate”, [online], [searched on Sep. 15, 2011], Internet <URL:http://genjix.ddo.jp/home/daijin/xor/>; and Constantinos Dovrolis, “CMOS Circuit Design and Accusim Simulations”, [online], University of Wisconsin, [searched on Sep. 15, 2011], Internet <URL:http://pages.cs.wisc.edu/˜david/courses/cs755/cs755/tutorials/tutorial5/tutorial5.html>
However, the XOR gate circuits that have so far been known have various problems, including: a larger number of elements, which leads to an increase in circuitry area; a larger number of transistors that signals pass through, which results in an increase in delay; and the circuits themselves not having a driver capability, causing waveforms to become dull. Therefore, there is the need for an XOR gate circuit that can solve the above problems.